The present invention relates generally to clock and data recovery circuits and, more particularly, to clock and data recovery circuits operable without an external reference clock.
Although processing circuitry often processes data in a parallel manner, the data are often communicated between points serially. Serial data may be transmitted without an explicit clock signal, for example, using a non-return-to-zero format. A receiver receiving the serial signal works to recover the transmitted data and a corresponding clock signal, with circuitry of the receiver performing such operations often termed a clock and data recovery circuit or more commonly a CDR.
Many clock and data recovery circuits use a reference clock signal in their operation, for example, to aid in clock recovery by having a reference clock signal with a frequency close to the data rate. The reference clock signal often comes from a reference clock in the form of a crystal oscillator or similar precision source. Provisioning of the reference clock may be expensive, occupy a large space, or have other undesirable impacts.
In some applications, serial data may be received at varying rates. In such applications, a CDR may be provided with multiple reference clock signals, one for each data rate, sourced from multiple reference clocks. This may substantially increase the expense of or space required for clock and data recovery circuits using reference clock signals.